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NCP3011, NCV3011
Boost Voltage
18
Voltage Ripple
16
14
12
10
8
6
4
2
0
Maximum Allowable Voltage
Maximum Boost Voltage
4.5
6.5
8.5
10.5
12.5
14.5 16.5 18.5
20.5
22.5
24.5
26.5
Input Voltage (V)
(Clarity on Boost Max and Ripple Def)
Figure 41. Boost Voltage at 80% Duty Cycle
Inductor Selection
When selecting the inductor, it is important to know the
input and output requirements. Some example conditions
are listed below to assist in the process.
Table 1. DESIGN PARAMETERS
Design Parameter Example Value
V OUT ) V LSD V OUT
D + [ D +
V IN * V HSD ) V LSD V IN
(eq. 8)
3.3 V
3 27.5% +
12 V
The ratio of ripple current to maximum output current
simplifies the equations used for inductor selection. The
Input Voltage
(V IN )
9 V to 18 V
formula for this is given in Equation 9.
Nominal Input Voltage
Output Voltage
(V IN )
(V OUT )
12 V
3.3 V
ra +
D I
I OUT
(eq. 9)
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
(VIN RIPPLE )
(VOUT RIPPLE )
(I OUT )
(Fsw)
300 mV
50 mV
8A
400 kHz
The designer should employ a rule of thumb where the
percentage of ripple current in the inductor lies between
10% and 40%. When using ceramic output capacitors the
ripple current can be greater thus a user might select a higher
ripple current, but when using electrolytic capacitors a lower
F +
1
V OUT
A buck converter produces input voltage (V IN ) pulses that
are LC filtered to produce a lower dc output voltage (V OUT ).
The output voltage can be changed by modifying the on time
relative to the switching period (T) or switching frequency.
The ratio of high side switch on time to the switching period
is called duty cycle (D). Duty cycle can also be calculated
using V OUT , V IN , the low side switch voltage drop V LSD ,
and the High side switch voltage drop V HSD .
(eq. 6)
T
ripple current will result in lower output ripple. Now,
acceptable values of inductance for a design can be
calculated using Equation 10.
L + @ (1 * D) 3 3.3 m H
I OUT @ ra @ F SW
(eq. 10)
3.3 V
+ @ (1 * 27.5%)
8 A @ 23% @ 400 kHz
The relationship between ra and L for this design example
is shown in Figure 42.
D +
T ON
T
( * D +
T OFF
T
(eq. 7)
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